Field of the Invention
The invention relates to a circuit configuration for generating even-numbered duty factors with an odd-numbered division n of a symmetrical clock signal.
In general, in many systems symmetrical clock pulses are required. An example thereof is low-harmonics clock generation in high-frequency systems in mixers, modulators, demodulators, etc. In division with an odd-numbered divisor factor n=3, 5, 7, 9, etc., typical divider circuits in general produce output clock pulses with an asymmetrical duty factor: ##EQU1##
In general, the duty factor can be described by the following formula: ##EQU2##